1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the formation of barrier layer for interconnects and more particularly for formation of a copper and silicon and nitrogen containing barrier layer.
2) Description of the Prior Art
Copper metallization is increasingly being used for advanced semiconductor device integrated circuit fabrication including semiconductor features having sub-quarter micron linewidths and high aspect ratios to larger features such as bonding pads. Copper and its alloys have lower resistivity and better electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving device reliability together with higher current densities and increased signal propagation speed. While several processing difficulties related to forming copper semiconductor features have been overcome, several problems remain, especially in the areas of current leakage between copper interconnects and the increased tendency of copper to electro-migrate through low-k porous dielectric insulating layers.
In forming a copper semiconductor feature, typically a relatively pure (undoped) copper material is deposited to fill an anisotropically etched opening, to form, for example a copper damascene or dual damascene structure. Copper electro-chemical plating (ECP) is a preferable method for depositing copper to achieve superior step coverage of sub-micron etched features. The deposited copper layer is then planarized to remove excess copper overlying the feature level by chemical mechanical polishing (CMP).
One problem affecting copper metallization is the tendency of copper to easily form oxides of copper, for example CuO or CuO2, upon exposure to oxidizing environments including humid environments. According to prior art processes, following the copper CMP process the exposed copper is protected by depositing overlying layers and/or storing in controlled environments to prevent copper oxidation. The formation of copper oxides increases the electrical resistance of the interconnect lines and reduces adhesion of overlying deposited layers. To form the next level of the device, a metal nitride layer which functions as an etching stop layer in formation of metal interconnect features such as vias or dual damascenes in overlying dielectric insulating layers, is typically deposited over the exposed copper following a CMP process. The overlying etching stop layer is also intended to act to prevent further copper oxidation and to reduce electro-migration of copper.
The dual goals of preventing copper electro-migration and preventing cross-interconnect current leakage have not been adequately solved for several reasons. For example, porous silicon oxide based low-K dielectric insulating layers having an interconnecting porous structure have exhibited reduced adhesion to overlying layers, for example etch stop layers, and have increased the tendency of integrated circuit damascene features, such as copper interconnects, to exhibit increased current leakage and electro-migration of copper ions. For example, a phenomenon known as time dependent dielectric breakdown (TDDB) is believed to result from charge accumulation due to slow current leakage over time along micro-cracks in the low-K dielectric insulating layers and along cracks developed along poorly adhering material interfaces. As low-K materials become even more porous in an effort to achieve lower the dielectric constants, they have coincidentally become increasing mechanically weak, frequently resulting in micro-cracking and poor adhesion at material interfaces thereby increasing both current leakage and Cu electromigration. As a result, electrical performance and device reliability of semiconductor devices is compromised.
Thus, there is a continuing need for novel semiconductor micro-circuitry manufacturing methods to improve the electrical performance of copper interconnect features including methods to reduce copper oxidation, improve adhesion of overlying layers, and to mechanically strengthen low-K dielectric insulating layers while maintaining low dielectric constants.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
US20050158999A1: Multi-step plasma treatment method to improve CU interconnect electrical performance—Plasma treating exposed copper surface and dielectric insulating layer for forming copper damascene structures, involves first plasma treatment with reduction gas and nitriding gas, and second plasma treatment with oxidizing gas—Inventor: Lin, Keng-Chu; Ping
US20050194683A1: Bonding structure and fabrication thereof—Inventor: Yu, Chen-Hua;—appears to show copper nitride protection layer on copper interconnect.
US20040115933A1: Jung—Methods of manufacturing a semiconductor device—Manufacture of semiconductor device, e.g. logic device, by filling contact hole with copper layer, planarizing, removing copper oxide layer, depositing copper barrier layer and upper insulating layer, and forming upper contact hole.
US20030214043A1: Semiconductor device—Semiconductor device comprises interconnect having second conductor film, e.g. titanium silicon nitride, being formed by chemical vapor deposition or atomic layer deposition Inventor: Saitoh, Toshio;
US20030073301A1: Multilayered diffusion barrier structure for improving adhesion property—Forming multi-layered diffusion barrier structure to improve adhesion between underlayer and deposited conducting layer by forming poorly electrical conducting adhesion-promoter layer over conducting diffusion barrier layer Inventor: Nguyen, Tue; Fremont, Calif., United
L S. Gosset, V. Arnal, S. Chhun, N. Casanova, M. Mellier, J. Ph. Reynard, X. Federspiel, J-F Guilaumond, L. Arnaud, J. Torres, sildes title. Integration and Characterization of a self aligned barrier to Cu diffusion based on copper silicide, apparently Advance metallization conferences (AMC) 2003.